In a digital synchronous system, effective clock distribution is essential for the system to work properly. Unduly slow propagation of a clock signal may limit the ability of a system's components to maintain adequate synchrony with each other. Moreover, a degraded clock signal can cause the system to malfunction completely, even with otherwise flawless design and components. With reference to FIG. 1, a representative clock distribution line 100 includes a reference clock signal 102 having a low logical level VL and a high logical level VH, a clock input buffer or driver 104. The distribution line 100 has an intrinsic resistance (R) and capacitance (C), 106, and a load capacitance 108 at the receiving end. The clock signal 102 is completely specified by a periodic high and low voltage levels (VH and VL), ideally with a square waveform.
When the resistance R of the line is comparable to or larger than the ON resistance of the driver, the propagation delay td is proportional to the RC time constant value. Because both resistance R and capacitance C increase linearly with length, this propagation delay td increases proportionally to the square of the line length. The degradation of the clock signal 102 is caused by the RC time constant of the clock distribution line 100 connecting the input buffer 104 to the gates having load capacitance CL 108. The clock signal 102 suffers degradation to the point that its original high VH and low VL values are distorted out of their original values. This is illustrated by an output clock signal 110. The RC component in the distribution line 100 acts as a low pass filter that causes the clock signal 102 to have a rise time and fall time proportional to the time constant RC. As a result, the clock signal 102 does not retain the original clock signal waveform. Therefore, a clock distribution network that minimizes propagation delay and signal degradation of a clock signal is needed.
There exist different approaches attempting to solve the above problem. Each approach depends on different intrinsic resistance and capacitance values of the clock distribution line 106. In one approach, the line is divided into smaller sections so that the time delay td is approximately linear with length, instead of the square of the length. With reference to FIG. 2A, the clock distribution line 200A is divided into k segments. The objective of this prior art approach is to find the optimum number of segments k that will minimize the propagation delay td.
Assume that total line resistance is R and total line capacitance is C. Each segment of the line is bounded by a minimum size inverting buffer or driver 204A with a characteristic input capacitance Ci, 202A, and a characteristic output impedance Ro, 206A. Each segment also has a distributed RC characteristic 208A. The distributed resistance Rs, 208A, of each segment equals to R/k, and the distributed capacitance Cs of each segment equals to C/k, assuming all segments are of the same length. The 50% propagation delay (the time at which Vout/Vin=0.5 in FIG. 3) can be expressed as T—50%=k[0.7R0(Cs+Ci)+Rs(0.4Cs+0.7Ci)], where the factor 0.7 refers to the RC term made of lumped resistance and capacitance (here R0 and Ci) and the factor 0.4 refers to the RC term made of a distributed resistance and capacitance (here Rs and Cs). The minimum value of T—50% gives the optimal k value, K_opt=sqrt{0.4 RC/0.7R0Ci}. For this optimal k value, the delay of a single segment connecting two inverters is equal to that of the single inverter, 0.4RsCs=0.7R0Ci.
With reference to FIG. 2B, in another approach, the propagation delay td can be further improved by increasing the size of the repeaters 204B by a factor h. The input capacitance 202B is now hCi, the output impedance 201B is now Ro/h, and the distributed RC component 208B remains unchanged. In this case, the optimal values for k and h become: K_opt=sqrt{0.4RC/0.7R0Ci}, and H_opt=sqrt{R0C/RCi}.
FIG. 3 illustrates the effect of lumped and distributed RC characteristic of clock distribution lines on the clock signal 300. In FIG. 3 the effect of the lumped RC is worse than that of the distributed RC on the clock signal 300. It takes the output voltage of a received clock signal 0.7 RC of time to reach 0.5 of its high logic value for a lumped-RC line 302, while it only takes the output voltage only 0.4 RC to reach the same level for a distribution-RC line 304. The severe effect of a lumped RC line 302 on the clock signal is ameliorated by the approach taken in FIG. 2B of increasing the repeater by an factor of h.
With reference to FIG. 4, another approach uses, instead of a single-inverter repeaters, repeater drivers made up of pairs of inverters 402 and 404 connected in series. In this way, the polarity of the clock signal traveling along the distribution line segment 406 remains the same at any point along the clock distribution line 400.
In all of the approaches described above, the repeater structure needs the clock signal received at a repeater input to cross the threshold of the inverter in order to work. If the RC value of the distribution line is very high, the k_opt value will be great and the minimum propagation delay at this optimum value will still be large.
An object of the present invention is to provide repeater structure for a clock distribution line that reduces the total propagation delay compared to prior repeater structure.